Keynote Speaker
Cristina Silvano
Full Professor at Politecnico di Milano
Title: Energy-Efficient Accelerators for AI on the Edge
Abstract
Hardware accelerators play a central role in enabling artificial intelligence (AI) workloads on high-performance computing (HPC) systems and in data centers, providing the computational capability required to process large datasets and train increasingly complex models. At the same time, the growing demand to deploy AI directly on edge devices—such as embedded systems, mobile platforms, and Internet-of-Things (IoT) devices—has shifted attention toward highly energy-efficient hardware solutions.
This talk surveys hardware accelerators across the full computing spectrum, from large-scale HPC systems to resource-constrained edge platforms, and discusses their impact on accelerating AI workloads through reduced execution time and improved energy efficiency. Particular emphasis is placed on techniques for mapping AI kernels onto energy-efficient Neural Processing Units (NPUs), as well as architectural approaches for tightly integrating Digital In-Memory Computing (DIMC) modules within NPUs to further enhance performance and energy efficiency.
Bio
Cristina Silvano is a Full Professor of Computer Architecture at Politecnico di Milano, where she holds the Chair of the Research Area on Computer Science and Engineering. In 2022, she was the promoter of the M. Sc. degree in HPC Engineering at Politecnico di Milano, the first program of its kind in Italy. In 2022, she has been appointed as member of the National Technical Committee on Semiconductor Technologies appointed by the Italian Ministry of University and Research. Currently, she is the leader of the flagship project on Hardware Accelerators of the Italian National Research Center for High Performance Computing. She has been Scientific Coordinator of three European research projects (ANTAREX, 2PARMA and MULTICUBE). Her research activities are in the areas of computer architecture and EDA, with focus on design space exploration of energy-efficient accelerators for deep neural networks and application autotuning for HPC. She has published more than 200 peer-reviewed papers, six books, and some patents in collaboration with Group Bull and STMicroelectronics. Since 2017, she is an IEEE Fellow for her contributions to energy-efficient computer architectures.
Invited Speakers
Nicholas Fraser
AMD Research and Advanced Development (RAD), Dublin
Title: Achieving Highly Accurate, Heavily Quantized Neural Networks
Abstract
Quantization of neural networks (NNs) is a key aspect of achieving high-performance neural network deployments. However, given the diversity neural network topologies and applications, it's often not obvious how best to approach quantization for a given problem. In this talk, we try address this gap by decomposing the quantization process into 4 steps: 1) pre-quantization transformations, i.e., error mitigation before quantization; 2) the simulation of low-precision datatypes with neural network models; 3) post-quantization accuracy recovery, i.e., error recovery after quantization; and 4) model export for fast deployment.
By decomposing the quantization process into these steps, we aim to equip model owners with the knowledge they need to understand what may apply to their own models. Finally, we explain how all-of-the-above steps can achieved through Brevitas, our PyTorch-based open-source neural network quantization library, designed for quantization research.
Bio
Nicholas J. Fraser received the PhD degree at The University of Sydney, Australia in 2020. Currently, he's a Research Scientist at AMD Research and Advanced Development (RAD), Dublin, Ireland, where he has conducted neural network quantization research for ~10 years and is project lead for the development of Brevitas, a PyTorch-based open-source neural network quantizer. His main research interests include: neural network quantization, software / hardware co-design of neural network topologies / accelerators, and audio signal processing..
Jacques Pienaar
Title: Breaking the Silos: How MLIR and CIRCT are Democratizing the AI Hardware Stack
Abstract
The traditional EDA landscape is characterized by semantic gaps between high-level algorithmic intent and physical implementation. As the industry pivots toward specialized AI accelerators, this disconnected workflow has become a critical bottleneck. Furthermore, hardware companies today face a "matrix of constraints": creating a competitive AI accelerator requires not just silicon, but a software stack that can keep pace with rapidly evolving research. Historically, this has resulted in fragmented, brittle toolchains that fail to unlock the hardware's potential. MLIR provides the escape velocity needed to break this cycle. This talk traces the evolution of MLIR from a software compiler framework to the backbone of an open hardware ecosystem. We will discuss the role of CIRCT in standardizing hardware description, the emergence of intermediate languages like Calyx and Allo for accelerator generation, and the importance of unified infrastructure for interoperability. By aligning on shared Intermediate Representations, the industry is moving from ad-hoc optimization to a converged methodology where software compilers and hardware generators speak the same language. The open development process, shared infrastructure, and interoperability through MLIR create an environment that matches hardware and software development velocities, enabling a new era for heterogeneous computing.
Bio
Jacques Pienaar serves as a Senior Staff Software Engineer at Google, where he has dedicated over ten years to architecting infrastructure for modern machine learning. In his current capacity as a lead within the ML Compilers and Systems Research team, Dr. Pienaar focuses on the acceleration and simplification of high-performance model deployment across distributed, heterogeneous compute platforms.
As a co-founder of Multi-Level Intermediate Representation (MLIR) and a foundational engineer for XLA, Dr. Pienaar has contributed to the development of industry-standard technologies for optimizing machine learning workloads. His professional background includes leading the TensorFlow graph optimization compiler initiative and extensive experience in developing optimization targets for a diverse range of environments, including custom hardware, data centers, and commodity edge devices.