Keynote Speaker
Alex Ramirez
Senior Staff Engineer at Google
Title: ML training scalability challenges
Bio
I am currently Senior Staff Engineer at Google, where I design, develop, and deliver high performance accelerator systems like the YouTube Video (trans)Coding Unit (VCU), or the ML infrastructure powering Gemini. Before that, I was Principal Research Scientist at NVIDIA in the Architecture group, associate professor at UPC, and Research Manager at the Barcelona Supercomputing Center.
I have a BsC ('95), MsC ('97) and PhD ('02, awarded the UPC extraordinary award to the best PhD in computer science) in Computer Science from the Universitat Politecnica de Catalunya, Barcelona, Spain. I have been a summer student intern with Compaq's Western Research Laboratory in Palo Alto, California for two consecutive years ('99-'00), and with Intel's Microprocessor Research Laboratory in Santa Clara ('01). I was awarded the first edition of the Agustin de Betancourt Award to a Young Researcher by the Spanish Royal Academy of Engineering in 2010.
I have co-authored more than 150 papers in international refereed conferences and journals, and supervised 10 PhD students. My research interests include energy efficient supercomputing, heterogeneous multicore architectures, hardware support for programming models, and simulation techniques.
Invited Speakers
Juan Gomez Luna
Senior Research Scientist at NVIDIA
Title: Accelerating Access to Data Storage and Services in the Age of AI
Abstract
Access to data storage and data services for GPUs has traditionally relied on the host CPU. While this approach might still be efficient for regular workloads and datasets that can be evenly partitioned, there are emerging applications (e.g., graph and data analytics, graph neural networks, recommender systems) that have a more irregular and data-dependent behavior. With the traditional approach, these workloads suffer from CPU-GPU synchronization, I/O traffic amplification, and long CPU latencies. In this talk, we will introduce GPU-initiated access to storage and services, which can efficiently support these emerging applications.
Bio
Juan Gómez Luna is a senior research scientist at NVIDIA since 2023. He received the BS and MS degrees in Telecommunication Engineering from the University of Sevilla, Spain, in 2001, and the PhD degree in Computer Science from the University of Córdoba, Spain, in 2012. Between 2005 and 2017, he was a faculty member of the University of Córdoba. Between 2017 and 2023, he worked as a senior researcher and lecturer at professor Onur Mutlu's SAFARI Research Group at ETH Zürich. His research interests focus on GPU and heterogeneous computing, memory and storage systems, processing-in-memory, and hardware and software acceleration of medical imaging and bioinformatics. He is the lead author of PrIM, the first publicly-available benchmark suite for a real-world processing-in-memory architecture, and Chai, a benchmark suite for heterogeneous systems with CPU/GPU/FPGA.
Rosa M. Badia
Research Manager Barcelona Supercomputing Center
Title: Managing and optimizing the life-cycle of AI-HPC workflows
Abstract
While the TOP500 yearly reflects the increase in the size of the HPC systems, the computing paradigm is also extended to consider a continuum edge-to-cloud/HPC.
Furthermore, the user community is aware of the underlying performance and eager to leverage it by providing more complex application workflows. The trend in such applications is to combine traditional HPC modelling and simulation with data analytics and artificial intelligence.
Our recent research has focused on making easier the management and optimization of the whole life-cycle of these workflows, from development to deployment and operation. Our work is based on PyCOMPSs, a parallel task-based programming environment in Python. Based on simple annotations, it can execute sequential Python programs in parallel in HPC clusters and other distributed infrastructures.
PyCOMPSs has been extended to support tasks that invoke HPC applications and combine them with Artificial Intelligence and Data analytics frameworks.
The talk will present this recent research and development, including examples of application workflows and how their performance or accuracy of results has been improved.
Bio
Rosa M. Badia holds a PhD in Computer Science (1994) from the Technical University of Catalonia (UPC). She is the manager of the Workflows and Distributed Computing research group at the Barcelona Supercomputing Center (BSC, Spain). Her research has contributed to parallel programming models for multicore and distributed computing. Recent contributions have been focused in the area of the digital continuum, proposing new programming environments and software environment for edge-to-cloud/HPC. The research is integrated in PyCOMPSs/COMPSs, a parallel task-based programming distributed computing framework, and its application to developing large heterogeneous workflows that combine HPC, Big Data, and Machine Learning. The group is also doing research around the dislib, a parallel machine learning library parallelized with PyCOMPSs. Dr Badia has published nearly 200 papers on her research topics in international conferences and journals. She has been very active in projects funded by the European Commission and in contracts with industry. She has been the PI of the EuroHPC project eFlows4HPC.
She is a member of HiPEAC Network of Excellence. She received the Euro-Par Achievement Award 2019 for her contributions to parallel processing, the DonaTIC award, category Academia/Researcher in 2019 and the HPDC Achievement Award 2021 for her innovations in parallel task-based programming models, workflow applications and systems, and leadership in the high performance computing research community. In 2023, she has been invited to be a member of the Institut d'Estudis Catalans (Catalan academy).
Christos Bouganis
Professor of Intelligent Digital Systems, Imperial College London
Title: Deep Neural Networks in the Embedded Space: Opportunities and Challenges
Abstract
The talk will address the challenging task of designing FPGA-based
hardware accelerators for Convolutional Neural Networks (CNNs), with a particular
focus on the embedded space. It will highlight the opportunities offered by
reconfigurable computing, specifically the advantages of design customization, and
delve into the challenges faced when mapping large CNN models onto embedded
FPGA devices.
I will share my research team’s efforts in tackling these challenges and provide an in-
depth overview of our fpgaConvNet toolchain. This toolchain addresses key
obstacles in the design process, enabling the generation of high-performance CNN
accelerators that achieve state-of-the-art results.
Bio
Christos-Savvas Bouganis is a Professor of Intelligent Digital Systems in
the Department of Electrical and Electronic Engineering, Imperial College London,
U.K. He is leading the iDSL group at Imperial College,
with a focus on the theory and practice of reconfigurable computing and design
automation, mainly targeting the domains of Machine Learning, Computer Vision,
and Robotics.