Keynote Speakers
Invited Speakers
Miquel Moretó
Barcelona Supercomputing Center (BSC)
Title: Designing HPC Architectures to Accelerate AI at BSC
In this 9th AccML workshop, we aim to bring together researchers working in Machine Learning and System Architecture to discuss requirements, opportunities, challenges and next steps in developing novel approaches for machine learning systems.
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The remarkable performance of machine learning across application areas (natural language processing, computer vision, games, etc.) has driven the emergence of heterogeneous architectures — and the compilers, runtime systems, libraries and tools around them — to accelerate these workloads. Since deep learning models are memory- and compute-intensive for both training and inference, acceleration cuts energy consumption in data centers and brings models to smaller devices at the edge. Meanwhile, models keep diversifying, from CNNs to Vision Transformers and Large Language Models, continually challenging computer architecture, the system stack, and programming abstractions. This calls for a dedicated forum on emerging acceleration techniques for machine learning, and on applying machine learning to build better computing systems.
The workshop brings together researchers and practitioners working on computing systems for machine learning, and using machine learning to build better computing systems, to raise awareness of existing efforts, foster collaboration, and enable the free exchange of ideas.
This builds on the success of our previous events:
Topics of interest include (but are not limited to):
Novel ML/AI systems: heterogeneous multi/many-core systems, GPUs, NPUs/TPUs, ASICs, FPGAs, and chiplet-based accelerators;
Software ML/AI acceleration: programming models, languages, primitives, libraries, compilers, runtimes, and frameworks;
Novel ML/AI hardware accelerators and associated system software;
Emerging semiconductor, near-/in-memory, analog, photonic, and neuromorphic technologies for ML/AI hardware acceleration;
ML/AI for the design, optimization, autotuning, and management of hardware, compilers, runtimes, and systems;
Cloud, data-center, edge, embedded, and on-device ML/AI computing: hardware and software to accelerate training and inference;
Hardware/software co-design techniques for efficient model training and inference, including quantization, sparsity, pruning, compression, efficient attention, and distillation;
Training, fine-tuning, serving, and deployment of foundation models, LLMs, multimodal models, large GNNs, recommender systems, agentic AI, and retrieval-augmented generation;
Submission deadline: November 13, 2026 (end of day)
Notification to authors: November 27, 2026
Papers should be in double column IEEE format of between 4 and 8 pages including references. Papers should be uploaded as PDF and not anonymized.
Get the IEEE templatesPapers will be reviewed by the workshop's technical program committee according to criteria regarding a submission's quality, relevance to the workshop's topics, and, foremost, its potential to spark discussions about directions, insights, and solutions on the topics mentioned above. Research papers, case studies, and position papers are all welcome.
In particular, we encourage authors to keep the following options in mind when preparing submissions:
Tentative Research Ideas: Presenting your research idea early one to get feedback and enable collaborations.
Works-In-Progress: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and generally spark discussion.
Barcelona Supercomputing Center (BSC)
Title: Designing HPC Architectures to Accelerate AI at BSC
| Time | January 2027 (TBA) |
|---|---|
| TBA | The full program will be announced after the notification to authors. |
